This invention relates generally to methods and apparatus for on-chip testing of integrated circuits ("IC's"), and more particularly to a method and apparatus for enabling and disabling access to IC test modes and test functions.
Very large-scale integrated (VLSI) circuit chips manufactured with modern IC technologies routinely include hundreds of thousands of circuit devices (e.g., transistors). As the number of on-chip devices increases, the complexity of circuit permutations increases. To adequately test VLSI chips built-in test devices commonly reside on the IC substrate with operational circuitry.
Resident test circuits often are accessed via the same chip pins as the operational circuits. To initiate a test operation, a prescribed signal pattern is applied to the chip under test. To avoid inadvertent entry into a test mode, application of a known out-of-spec voltage (e.g., "super-voltage") to a prescribed pin may be required throughout the test procedure. There is concern, however, with continually applying an out-of-spec voltage. Specifically, applying an out-of-spec voltage for an extended period of time can damage the IC and its internal circuits. Another concern is that leakage specifications for the prescribed pin may not be met. Yet another concern is that the out-of-spec voltage may alter the electrical properties of the IC substrate during the time the voltage is applied. If so, then functional and performance results occurring in a test mode may differ from those in normal operating modes. Another concern is that the out-of-spec voltage level may fall during a test procedure so as to be within specification. This inadvertently terminates the test mode. When simultaneously testing many IC's, uneven power signal distribution will cause such variation of the out-of-spec voltage, terminating the test mode for one or more IC's. Accordingly, there is need for an alternate manner of preventing inadvertent entry into (and out of) a test mode.